Dry self-alignment for batch-assembly of chips

This paper reports experimental results on a dry self-alignment method using a combination of electrostatic fields and mechanical traps to position microsystem chips on a carrier wafer. The electrostatic fields were created by charging SiO₂ layers patterned on the carrier and the chips. Pedestal-cavity mating-structures were employed as spacers to avoid premature sticking and ensure unique alignment position. Vertical vibration was applied to stochastically move the chips. During 10 repetitive experiments, 16 dummy-chips with dimension 2times2 mm were accurately aligned on the carrier within an average of 30 seconds and standard deviation of 11 seconds. This method can be used to batch assemble different types of chips, e.g. by carrier-to-carrier transfer, in dry environment with high accuracy and low cost.