A VLSI neural network classifier based on integer-valued weights

Author

Draghici, Sorin ; Miller, Damon A.

Author_Institution

Dept. of Comput. Sci., Wayne State Univ., Detroit, MI, USA

Volume

4

fYear

1999

fDate

1999

Firstpage

2419

Abstract

The VLSI-friendly constraint based decomposition (VCBD) algorithm guarantees construction of neural network classifiers with a user-chosen maximum neuron fan-in and weight values confined to a narrow band of integers. Networks with these characteristics can be efficiently implemented in VLSI. This paper presents the design of a CMOS neuron that fully exploits the characteristics of solutions produced by VCBD. The limited integer weight range enables efficient use of current-mode techniques for addition and multiplication operations within the neuron. Weights are stored in digital form without quantization error. A simple current comparator is used to provide the neuron output. Circuit operation has been verified using SPICE and these simulation results are included

Keywords

CMOS analogue integrated circuits; VLSI; current comparators; current-mode logic; neural chips; pattern classification; CMOS neuron; SPICE; VCBD algorithm; VLSI neural network classifier; VLSI-friendly constraint based decomposition; addition operations; current-mode techniques; integer-valued weights; multiplication operations; user-chosen maximum neuron fan-in; Artificial neural networks; Circuits; Computer science; Laboratories; Milling machines; Neural network hardware; Neural networks; Neurons; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Neural Networks, 1999. IJCNN '99. International Joint Conference on

Conference_Location

Washington, DC

ISSN

1098-7576

Print_ISBN

0-7803-5529-6

Type

conf

DOI

10.1109/IJCNN.1999.833448

Filename

833448