Title :
A feasibility study of on-wafer wireless testing
Author :
Park, Piljae ; Yue, C. Patrick
Author_Institution :
Dept. of ECE, Univ. of California, Santa Barbara, CA
Abstract :
The feasibility of on-wafer wireless test is assessed in this paper. By replacing expensive high-frequency probe cards with wireless data link, testing cost can potentially be lowered. Key elements for wireless test at the wafer level include on-chip antenna and RF transceivers. A 24-GHz on-chip folded dipole antenna has been designed to fit in the scribe-lines between the silicon dies. The measured antenna gain shows -22.6 dBi. The power budget for a data link between a wafer with on-chip antenna and a tester equipped with high-gain horn antenna is presented. Our finding verifies that the required SNR and antenna bandwidth for wireless test can be achieved. Based on the measured antenna characteristics, several wireless test examples are illustrated.
Keywords :
dipole antennas; horn antennas; integrated circuit testing; transceivers; RF transceivers; high-frequency probe cards; high-gain horn antenna; on-chip antenna; on-chip folded dipole antenna; on-wafer wireless testing; scribe-lines; silicon dies; testing cost; wireless data link; Antenna measurements; Costs; Dipole antennas; Gain measurement; Horn antennas; Probes; Radio frequency; Silicon; Testing; Transceivers; CMOS on-chip antenna; Wireless test; folded dipole antenna;
Conference_Titel :
VLSI Design, Automation and Test, 2008. VLSI-DAT 2008. IEEE International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-1616-5
Electronic_ISBN :
978-1-4244-1617-2
DOI :
10.1109/VDAT.2008.4542472
