Effects of parameter variations on timing characteristics of clocked registers

Violations in the timing constraints of a clocked register can cause a synchronous system to malfunction. The effects of parameter variations on the timing characteristics of registers that determine the timing constraints are investigated in this paper. The sensitivity of the setup time and data propagation delay on parameter variations is demonstrated for three different register designs that represent different tradeoff choices between performance and power dissipation. The robustness of each register design under variations in power supply voltage, temperature, and gate oxide thickness is discussed