• DocumentCode
    1854697
  • Title

    Self-assembled nanowire-on-insulator (SANOI) for nano-chip technology

  • Author

    Yu, Bin ; Calebotta, Gabe ; Yuan, Kenneth ; Meyyappan, Meyya

  • Author_Institution
    Center for Nanotechnol., NASA Ames Res. Center, Moffett Field, CA, USA
  • fYear
    2005
  • fDate
    11-15 July 2005
  • Firstpage
    742
  • Abstract
    One-dimensional semiconducting nanowires (Si or Ge) directly synthesized on insulator layer by chemical method provide a viable technology analogous to silicon-on-insulator (SOI) and germanium-on-insulator (GOI), yet presenting much better chip design/integration flexibility, structural scalability, and cost-effectiveness. The new technology, called self-assembled nanowire-on-insulator (SANOI), illustrates a good example of how bottom-up nanotechnology based on inexpensive chemistry may provide solution to some of the most daunting challenges in the conventional silicon CMOS scaling.
  • Keywords
    elemental semiconductors; germanium; nanotechnology; nanowires; self-assembly; silicon-on-insulator; Ge; SOI; Si; germanium-on-insulator; insulator layer; nanochip technology; one-dimensional semiconducting nanowires; self-assembled nanowire-on-insulator; silicon CMOS scaling; silicon-on-insulator; CMOS technology; Chemical technology; Chip scale packaging; Insulation; Nanotechnology; Nanowires; Scalability; Self-assembly; Semiconductivity; Silicon on insulator technology;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Nanotechnology, 2005. 5th IEEE Conference on
  • Print_ISBN
    0-7803-9199-3
  • Type

    conf

  • DOI
    10.1109/NANO.2005.1500637
  • Filename
    1500637