System-on-chip (SoC) requires IC and package co-design and co-verification

The accelerating pace of the technology race towards more complex integrated systems is leading to a series of drawbacks: awfully high pin-count and clock-speed, increasing mask costs and wafer yield issues due to mixing device technologies, and unachievable time-to-market. In recent years, major breakthroughs have occurred in packaging technology, which have led to the industrialization of several kinds of new packages, more powerful, and yet more flexible. The combination of these two technological trends is driving the evolution of IC and package design and verification, which must be considered, more and more, as a single whole. For this evolution, to be successful, however, three ingredients are required: a change in methodology, the availability of a new category of EDA tools, and a major shift in the profile of the designers and engineers involved.