• DocumentCode
    1854981
  • Title

    Single reference continuous rate clock and data recovery from 30 Mbit/s to 3.2 Gbit/s

  • Author

    Frambach, Jan-Peter ; Heijna, Roeland ; Krosschell, Rob

  • Author_Institution
    Philips Semicond., Nijmegen, Netherlands
  • fYear
    2002
  • fDate
    2002
  • Firstpage
    375
  • Lastpage
    378
  • Abstract
    Today´s networks encompass a myriad of bit rates, both new appearing rates as well as legacy ones. To cover all these bit rates, a continuous rate chip-set was developed, containing a continuous rate clock and data recovery, capable of recovering any bit rate between 30 Mbit/s and 3.2 Gbit/s. While using only one single reference frequency, a frequency acquisition loop, based on a fractional-N divider and a frequency window detector, provides 4.8 Hz frequency resolution. A built-in PRBS generator provides for high frequency testing.
  • Keywords
    detector circuits; digital communication; optical communication equipment; optical fibre networks; reference circuits; synchronisation; 30 Mbit/s to 3.2 Gbit/s; PRBS generator; continuous rate chip-set; frequency acquisition loop; frequency resolution; frequency window detector; high frequency testing; single reference continuous rate clock and data recovery; Bit rate; Clocks; Frequency conversion; Frequency locked loops; Optical frequency conversion; Phase detection; Phase frequency detector; Synthesizers; Testing; Voltage-controlled oscillators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002
  • Print_ISBN
    0-7803-7250-6
  • Type

    conf

  • DOI
    10.1109/CICC.2002.1012847
  • Filename
    1012847