Development of verification envioronment for SPI master interface using SystemVerilog

System-level verification with scalable and reusable components provides a solution for current complex SOC verification and SystemVerilog with OOP is one of the most promising language to develop a complete verification environment with constrained random testing, functional coverage and assertions. In this paper, a uniform verification environment for SPI master interface is developed using SystemVerilog after a comprehensive analysis of the verification plan. The proposed multi-layer testbench is comprised of APB driver, SPI slave, scoreboard, checker, coverage analysis and assertions, which are implemented with different properties of SystemVerilog. Furthermore, constrained random testing vectors are generated automatically and driven into the DUT for higher functional coverage. The verification result shows the effectiveness of the proposed verification environment, which is of great feasibility for further extension and reuse.