Title :
A study of Through Silicon Via impact to 3D Network-on-Chip design
Author :
Xu, Thomas Canhao ; Liljeberg, Pasi ; Tenhunen, Hannu
Author_Institution :
Dept. of Inf. Technol., Univ. of Turku, Turku, Finland
Abstract :
The adoption of a 3D Network-on-Chip (NoC) design depends on the performance and manufacturing cost of the chip. Therefore, a study of Through Silicon Via (TSV), that connects different layers of a 3D chip, is crucial. In this paper, we analysis the impact of TSV design in 3D NoCs. A 3D NoC with five layers is modeled based on modern 2D chips. We discuss the TSV number required for a 3D NoC. Different placements of half and quarter layer-layer connections are explored. We present benchmark results using a cycle accurate full system simulator based on realistic workloads. Experiments show that under different workloads, the average network latencies in full and half layer-layer connection are reduced by 5.24% and 2.18% respectively, compared with quarter design. Our analysis and experiment results provide a guideline for designing TSVs in 3D NoCs to leverage the tradeoff between performance and manufacturing cost.
Keywords :
integrated circuit design; integrated circuit interconnections; network-on-chip; 2D chips; 3D network-on-chip design; TSV design; manufacturing cost; through silicon via; Computer architecture; Manufacturing; Routing; Solid modeling; System-on-a-chip; Three dimensional displays; Through-silicon vias;
Conference_Titel :
Electronics and Information Engineering (ICEIE), 2010 International Conference On
Conference_Location :
Kyoto
Print_ISBN :
978-1-4244-7679-4
Electronic_ISBN :
978-1-4244-7681-7
DOI :
10.1109/ICEIE.2010.5559865
