Title :
A 2.5 V 10 b 120 MSample/s CMOS pipelined ADC with high SFDR
Author :
Yoo, Sang-Min ; Oh, Tae-Hwan ; Moon, Jung-Woong ; Lee, Seung-Hoon ; Moon, Un-Ku
Author_Institution :
Dept. of Electron. Eng., Sogang Univ., Seoul, South Korea
Abstract :
A 10 b multibit-per-stage pipelined ADC incorporating the merged-capacitor switching (MCS) technique achieves better than 53 dB SNDR at 120 MSample/s and 54 dB SNDR and 68 dB SFDR for input frequencies up to Nyquist at 100 MSample/s. The measured DNL and INL are ±0.40 LSB and ±0.48 LSB, respectively. The ADC fabricated in a 0.25 μm CMOS process, occupies 3.6 mm2 active die area and consumes 208 mW under a 2.5 V power supply.
Keywords :
CMOS integrated circuits; analogue-digital conversion; pipeline processing; switched capacitor networks; 0.25 micron; 10 bit; 2.5 V; 208 mW; CMOS pipelined ADC; DNL; INL; SNDR; flash ADCs; high SFDR; merged-capacitor switching technique; CMOS integrated circuits; Consumer electronics; Decoding; Energy consumption; Frequency; Logic; Modems; Moon; Sampling methods; Switched capacitor circuits;
Conference_Titel :
Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002
Print_ISBN :
0-7803-7250-6
DOI :
10.1109/CICC.2002.1012869
