Sub-50 nm T-gate pseudomorphic HEMTs using low temperature development method

This paper demonstrates the use of a low temperature development method as a second development stage in the sub-50 nm T-gate process for Al_0.25Ga_0.75As/In_0.2Ga_0.8As/GaAs pseudomorphic HEMTs. As the development temperature goes down, clearing doses for PMMA and PMMA-MAA are increased. This reduction of sensitivity in low temperature development reduces the detrimental effect on the second stage by the first exposure in the tri-layer (PMMA/PMMA-MAA/PMMA) T-gate process for HEMTs. Thus, both resolution and vertical profile are enhanced in this process. A 25 nm T-shaped resist profile was patterned and a 40 nm T-gate was fabricated after metal lift-off using low temperature development under a low 20 kV E-beam acceleration voltage condition. This method was used to successfully fabricate 40 nm T-gate pHEMTs with 580 mS/mm.