Title :
A 8-bit 200 MS/s interpolating/averaging CMOS A/D converter
Author :
Vandenbussche, J. ; Uyttenhove, K. ; Lauwers, E. ; Steyaert, M. ; Gielen, G.
Author_Institution :
Dept. of Electr. Eng., Katholieke Univ., Leuven, Heverlee, Belgium
Abstract :
A 8-bit 200MS/s 4-2 interpolating A/D converter is presented. A novel input stage was developed to enhance the dynamic performance. Static performance is enhanced using the averaging technique. The chip has been fabricated in a standard 0.35 μm CMOS process. An INL/DNL of 0.95/0.8 LSB was measured. An SNR figure of 44.3 dB was achieved at low frequencies: for a 30 MHz input signal an SNR figure of 43 dB was measured.
Keywords :
CMOS integrated circuits; analogue-digital conversion; integrated circuit design; interpolation; sample and hold circuits; 0.35 micron; 30 MHz; 44.3 dB; 8 bit; CMOS A/D converter; CMOS ADC; DNL; INL; SNR; architectural-level sizing; device-level sizing; dynamic performance enhancement; input stage; interpolating/averaging ADC; standard CMOS process; CMOS process; Capacitance; Energy consumption; Frequency measurement; Parallel processing; Power supplies; Preamplifiers; Rail to rail outputs; Semiconductor device measurement; Signal resolution;
Conference_Titel :
Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002
Print_ISBN :
0-7803-7250-6
DOI :
10.1109/CICC.2002.1012871
