DocumentCode :
1855329
Title :
Understanding MOSFET mismatch for analog design
Author :
Drennan, P.G. ; McAndrew, C.C.
Author_Institution :
Motorola Inc., Tempe, AZ, USA
fYear :
2002
fDate :
2002
Firstpage :
449
Lastpage :
452
Abstract :
This paper addresses misconceptions about MOSFET mismatch for analog design. Vt mismatch does not follow a simplistic 1/(√area) law, especially for wide/short and narrow/long devices, which are common geometries in analog circuits. Further, Vt and gain factor are not appropriate parameters for modeling mismatch. A physically based mismatch model can be used to obtain dramatic improvements in the prediction of mismatch. This model is applied to MOSFET current mirrors to show some non-obvious effects over bias, geometry, and multiple unit devices.
Keywords :
MOSFET; analogue integrated circuits; integrated circuit design; semiconductor device models; MOSFET current mirrors; MOSFET mismatch; analog IC design; bias; geometry; multiple unit devices; physically based mismatch model; Analog circuits; Analog integrated circuits; Costs; FETs; Geometry; MOSFET circuits; Mirrors; Permittivity; Resists; Solid modeling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002
Print_ISBN :
0-7803-7250-6
Type :
conf
DOI :
10.1109/CICC.2002.1012872
Filename :
1012872
Link To Document :
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