Title :
Low-voltage pipelined ADC using opamp-reset switching technique
Author :
Chang, Dong-Young ; Wu, Lei ; Moon, Un-Ku
Author_Institution :
Oregon State Univ., Corvallis, OR, USA
Abstract :
A low-voltage opamp-reset switching technique (ORST) which avoids clock boosting/bootstrapping, switched-opamp, and threshold voltage scaling is presented. The switching technique is applied to the design of a 10-bit 25 MSPS pipelined ADC. The prototype ADC demonstrates 55 dB SNR, 55 dB SFDR, and 48 dB SNDR at 1.4 V power supply. The ADC operates down to 1.3 V power supply (|VTH,P|=0-9 V) with 5 dB degradation in performance. Maximum operating frequency is 32 MSPS. The ORST is fully compatible with future low-voltage submicron CMOS processes.
Keywords :
CMOS integrated circuits; analogue-digital conversion; integrated circuit design; integrated circuit noise; operational amplifiers; pipeline processing; 0.9 V; 1.3 V; 1.4 V; 10 bit; ADC design; ADC power supply; ORST; SFDR; SNDR; SNR; clock boosting; clock bootstrapping; low-voltage CMOS processes; low-voltage pipelined ADC; maximum operating frequency; opamp-reset switching technique; performance degradation; switched-opamp; switching technique; threshold voltage scaling; Boosting; Breakdown voltage; CMOS process; CMOS technology; Capacitors; Circuit topology; Clocks; Sampling methods; Switches; Threshold voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002
Print_ISBN :
0-7803-7250-6
DOI :
10.1109/CICC.2002.1012877
