Title :
Technology trends and challenges for CMOS/system LSIs for the next 10-15 years
Author :
Kawamura, Seiichiro
Author_Institution :
Adv. Semicond. Res. Center, Tsukuba, Japan
Abstract :
There are many challenges which we will be facing in the next 10 to 15 years in developing a state-of-the-art CMOS technology for system LSIs. Among them, lithography, gate-stack, shallow junction and interconnect technologies are major ones. In this paper, these major challenges as well as "Design Crisis" and "Power Crisis" are discussed in detail from an ITRS (international Technology Roadmap for Semiconductors) perspective, and some potential solutions are described to overcome these challenges and crises.
Keywords :
CMOS integrated circuits; ULSI; VLSI; integrated circuit design; integrated circuit technology; nanolithography; system-on-chip; CMOS technology; ITRS perspective; ULSI; design crisis; gate-stack; interconnect technologies; international Technology Roadmap for Semiconductors; lithography; power crisis; shallow junction; system LSIs; system chips; CMOS technology; Delay; Electronic design automation and methodology; Integrated circuit interconnections; Large scale integration; Lithography; Logic circuits; Process design; Productivity; Threshold voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002
Print_ISBN :
0-7803-7250-6
DOI :
10.1109/CICC.2002.1012879
