Title :
A simulated annealing approach for high-level synthesis with reconfigurable functional units
Author :
Alves, J.C. ; Matos, J.S.
Author_Institution :
Fac. de Engenharia, Porto Univ., Portugal
Abstract :
In this paper, we present an application of the simulation annealing optimization algorithm to the problem of high-level synthesis of digital systems, targeted to architectures with run-time reconfigurable functional units. The scheduling, allocation and binding problems are treated simultaneously. Reconfiguration times and execution delays are taken into account, along with pipelined execution and precise clock cycles for consumption of each operand
Keywords :
circuit CAD; field programmable gate arrays; high level synthesis; scheduling; simulated annealing; allocation; binding problems; digital systems; high-level synthesis; optimization algorithm; pipelined execution; reconfigurable functional units; scheduling; simulated annealing; Clocks; Computational modeling; Computer architecture; Costs; Delay; Delay effects; Digital systems; Hardware; High level synthesis; Processor scheduling; Runtime; Simulated annealing;
Conference_Titel :
Circuits and Systems, 1995., Proceedings., Proceedings of the 38th Midwest Symposium on
Conference_Location :
Rio de Janeiro
Print_ISBN :
0-7803-2972-4
DOI :
10.1109/MWSCAS.1995.504440
