Title :
Test generation for current testing of bridging faults in CMOS VLSI circuits
Author :
Lee, Terry ; Hajj, Porahim N.
Author_Institution :
Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
Abstract :
An efficient automatic test pattern generator for IDDQ current testing of CMOS digital circuits is presented. The complete two-line bridging fault set is considered. Genetic algorithms are used to generate compact test sets. Experimental results for ISCAS85 and ISCAS89 benchmark circuits are presented
Keywords :
CMOS logic circuits; VLSI; automatic testing; fault diagnosis; genetic algorithms; integrated circuit testing; logic testing; CMOS; IDDQ current testing; ISCAS85 benchmark circuits; ISCAS89 benchmark circuits; VLSI; automatic test pattern generator; bridging faults; compact test sets; digital circuits; genetic algorithms; two-line bridging fault set; Automatic test pattern generation; Automatic testing; Benchmark testing; CMOS digital integrated circuits; Circuit faults; Circuit testing; Combinational circuits; Digital circuits; Genetic algorithms; Performance evaluation; Semiconductor device testing; Test pattern generators; Very large scale integration; Voltage;
Conference_Titel :
Circuits and Systems, 1995., Proceedings., Proceedings of the 38th Midwest Symposium on
Conference_Location :
Rio de Janeiro
Print_ISBN :
0-7803-2972-4
DOI :
10.1109/MWSCAS.1995.504443
