DocumentCode
1855607
Title
Optimized clock gating cell for low power design in nanoscale CMOS technology
Author
Durgam, Aniryudh Reddy ; Choi, Kwonhue
Author_Institution
Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL, USA
fYear
2013
fDate
26-28 Aug. 2013
Firstpage
85
Lastpage
88
Abstract
This paper discusses a novel clock gating cell (CGC) optimized for high performance and low power design. The conventional CGC is analyzed along with other low power implementations of the CGC that have previously been proposed. The new CGC topology is proposed and compared to the topologies previously introduced in terms of dynamic clock power, leakage, area and timing.
Keywords
CMOS logic circuits; clocks; logic gates; nanoelectronics; CGC topologies; clock gating cell; dynamic clock power; efficient circuit design; free running clock; leakage area timing; logic gates; low power design; nanoscale CMOS technology; power aware design; transistor number; Clocks; Inverters; Latches; Logic gates; Power demand; Topology; Transistors; Clock gating cell; clock gater; clock gating; local clock buffer; low power design;
fLanguage
English
Publisher
ieee
Conference_Titel
Quality Electronic Design (ASQED), 2013 5th Asia Symposium on
Conference_Location
Penang
Print_ISBN
978-1-4799-1312-1
Type
conf
DOI
10.1109/ASQED.2013.6643569
Filename
6643569
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