Title :
Tunable stochastic computing using layered synthesis and temperature adaptive voltage scaling
Author :
Gala, N. ; Devanathan, V.R. ; Visvanathan, V. ; Gandhi, V. ; Kamakoti, V.
Author_Institution :
Dept. of Comput. Sci. & Eng., Indian Inst. of Technol. Madras, Chennai, India
Abstract :
With increasing computing power in mobile devices, conserving battery power (or extending battery life) has become crucial. This together with the fact that most applications running on these mobile devices are increasingly error tolerant, has created immense interest in stochastic (or inexact) computing. In this paper, we present a framework wherein, the devices can operate at varying error tolerant modes while significantly reducing the power dissipated. Further, in very deep sub-micron technologies, temperature has a crucial role in both performance and power. The proposed framework presents a novel layered synthesis optimization coupled with temperature aware supply and body bias voltage scaling to operate the design at various “tunable” error tolerant modes. We implement the proposed technique on a H.264 decoder block in industrial 28nm low leakage technology node, and demonstrate reductions in total power varying from 30% to 45%, while changing the operating mode from exact computing to inaccurate/error-tolerant computing.
Keywords :
decoding; electronic engineering computing; stochastic processes; tuning; H.264 decoder block; error tolerant modes; layered synthesis; low leakage technology node; size 28 nm; temperature adaptive voltage scaling; tunable stochastic computing; Computer architecture; Delays; Logic gates; Mathematical model; Optimization; Stochastic processes; Adaptive Supply Voltage; Functional Criticality; Layered Synthesis; Low Power Computing; Power Grid; Stochastic Computing; Tunable Computing;
Conference_Titel :
Quality Electronic Design (ASQED), 2013 5th Asia Symposium on
Conference_Location :
Penang
Print_ISBN :
978-1-4799-1312-1
DOI :
10.1109/ASQED.2013.6643572