Title :
Binary canonic signed digit multiplier for high-speed digital signal processing
Author :
Lo lacono, D. ; Ronchi, Marco
Author_Institution :
Adv. Syst. Technol., STMicroelectronics, Agrate Brianza, Italy
Abstract :
This paper presents a novel high-speed binary CSD (BCSD) multiplier which takes advantage of the benefits coming from the canonic signed digit (CSD) number system, while overcoming the inherent overhead due to the CSD ternary representation. BCSD is a binary number system which allows representing any CSD number using the same word -length used by the two´s complement representation. Thus, multipliers which make use of the BCSD technique exhibit a considerable advantage especially when the multiplicand belongs to a set of coefficients stored in a memory in its BCSD notation, requiring in this case nothing but the BCSD decoding scheme which maps the BCSD number back into its CSD representation without introducing any substantial overhead.
Keywords :
digital arithmetic; digital signal processing chips; multiplying circuits; binary canonic signed digit multiplier; binary number system; canonic signed digit number system; decoding scheme; high-speed digital signal processing; word-length; Adaptive filters; Adaptive signal processing; Adders; Decoding; Digital signal processing; Encoding; Frequency synthesizers;
Conference_Titel :
Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on
Print_ISBN :
0-7803-8346-X
DOI :
10.1109/MWSCAS.2004.1354128