Scalable pipeline insertion in floating-point division and square root units

Division and square root are important operations in a number of data processing algorithms. They are inherently time consuming operations and can require a significant amount of resources when implemented in hardware. This work reports the development of scalable, floating-point (FP) division and square root operators with adjustable precision, range, and pipeline granularity. An algorithm for pipeline insertion was used for both operators, enabling speeds up to 204MFLOPS when implemented on a Xilinx Virtex II FPGA.