An efficient line based VLSI architecture for 2D lifting DWT

Author

Jung, Gab Cheon ; Jin, Duk Young ; Park, Seong Mo

Author_Institution

Dept. of Electron. Eng., Chonnam Nat. Univ., South Korea

Volume

2

fYear

2004

fDate

25-28 July 2004

Abstract

This paper presents a line based VLSI architecture for real time processing of 2D lifting discrete wavelet transform (DWT). The architecture computes lifting operation based on state space representation and uses RPA (Recursive Pyramid Algorithm) scheme. To improve hardware utilization, the filter that is responsible for column operations of the first level performs both the row and column operations of the second and following levels. As a result, the architecture has the 66.7%-88.9% hardware utilization and requires only 9 multipliers and 12 adders for biorthogonal (9,7)/(5,3) filter, which is a smaller hardware complexity compared to that of other architecture with comparable throughput.

Keywords

VLSI; computer architecture; discrete wavelet transforms; image processing; pattern recognition; real-time systems; recursive filters; state-space methods; 2D lifting DWT; adders; biorthogonal filter; computer vision; discrete wavelet transform; hardware complexity; hardware utilization; image compression; lifting operation; line based VLSI architecture; multipliers; object recognition; recursive pyramid algorithm; signal analysis; state space representation; very large scale integration; Band pass filters; Computer architecture; Discrete wavelet transforms; Filter bank; Filtering; Hardware; Image coding; Low pass filters; Very large scale integration; Wavelet transforms;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on

Print_ISBN

0-7803-8346-X

Type

conf

DOI

10.1109/MWSCAS.2004.1354140

Filename

1354140