Cluster-based thermal-aware 3D-floorplanning technique with post-floorplan TTSV insertion at via-channels

In 3D-IC architecture, thermal issues largely affect design reliability. The three-dimensional structure impedes heat dissipation and leads to high temperature when designs in execution. In this paper, we propose a cluster-based 3D-floorplanning approach to place modules based on the factors of area, wire-length, and power density. Then we construct a precise thermal conduction model to compute temperature distribution in terms of the resultant floorplan. The thermal-vias will be placed at some reserved regions, called via-channels, by analytical computation based on temperature distribution. The thermal-via insertion procedure will repeat until the peak temperature is acceptable. The experimental results show that our framework is able to effectively reduce the peak temperature in hot-spots based on a precise temperature computation model.