Automatic parallelism exploitation for FPL-based accelerators

The paper introduces the first complete programming framework for coarse grain dynamically reconfigurable accelerators and their application development. It includes a general model for cooperating host/accelerator platforms and a parallelizing compilation technique derived from it. The paper is an introduction illustrating these techniques and their principles by examples: a machine architecture and its application development framework performing a “software-only” accelerator implementation (synthesis). The paper discusses the exploitation of four different levels of parallelism during this compilation process for achieving optimized speedups and hardware resource utilization