Title :
Testing switched-current memory cells using DC stimuli
Author :
Renovell, M. ; Azaïs, F. ; Bodin, J.C. ; Bertrand, Y.
Author_Institution :
LIRMM, Univ. des Sci. et Tech. du Languedoc, Montpellier, France
Abstract :
The authors study the efficiency of a DC test for a memory cell, which is the elementary building block for switched-current circuits. Simulations are performed on two different cells. It is demonstrated that most of the hard faults are detected using one single input test current for the basic cascode memory cell, and two reverse-sign currents for the S2I cascode memory cell. This study is also extended taking into account different values for the short and open resistance
Keywords :
analogue storage; cellular arrays; fault diagnosis; integrated circuit testing; integrated memory circuits; switched current circuits; DC stimuli; DC test; cascode memory cell; hard faults; open resistance; reverse-sign currents; short resistance; single input test current; switched-current memory cells; Capacitors; Circuit faults; Circuit simulation; Circuit testing; Electrical fault detection; MOS devices; MOSFETs; Switches; Switching circuits; Voltage;
Conference_Titel :
Design of Mixed-Mode Integrated Circuits and Applications, 1999. Third International Workshop on
Conference_Location :
Puerto Vallarta
Print_ISBN :
0-7803-5588-1
DOI :
10.1109/MMICA.1999.833586
