Minimal area homogeneous logic circuits using nano-wires

This paper presents an homogeneous (array-based) approach for designing and manufacturing digital circuits using nanotubes/nano-wires. As "a strategy for developing integrated devices with many individual elements has yet to be formulated", it is evident that such an environment is a necessity for designing circuits using nano-wires. At logic level, a novel formulation for area reduction is proposed and solved in polynomial time using a heuristic technique. It is analyzed that ∼40% saving in the area of physical mask layout is possible due to the small diameter of nano-wires and the proposed area optimization approach.