Implementing proper ASIC design margins: a must for reliable operation

This paper presents some of the basic timing related design parameters for digital ASICs (propagation delay, operating frequency) where sufficient margin must exist to preclude operational failures caused by performance degradation from such effects as: aging, nuclear radiation, voltage, temperature and variability in processing. As ASICs and gate arrays become the standard building blocks for digital circuits and systems, reliability engineers must be aware of these parameters and methods for assuring proper design margin. The techniques utilized on a high reliability program to define and quantify the timing for their ASIC designs will be presented to illustrate these concepts. Although the specific examples shown are for CMOS/SOS devices, applying these or similar techniques can provide an optimization between ASIC performance and long term operational reliability for any ASIC technology