Title :
A CMOS low-jitter phase frequency detector for giga-bit/s clock recovery
Author :
Wang, Hui ; Nottenburg, Richard
Author_Institution :
Dept. of Electr. Eng.-Electrophys., Univ. of Southern California, Los Angeles, CA, USA
Abstract :
The PFD consists of a bang-bang Frequency Detector (FD) and a Phase Detector (PD) with analog outputs. The frequency acquisition range is over ±30%. The bang-bang FD disconnects itself from the loop once lock acquisition is achieved. The PFD was fabricated in a 0.5 μm CMOS process for 1 Gbit/s clock recovery. RMS jitter in the recovered 1 GHz clock is 7.4 ps
Keywords :
CMOS integrated circuits; detector circuits; mixed analogue-digital integrated circuits; synchronisation; telecommunication equipment; timing circuits; timing jitter; 0.5 micron; 1 Gbit/s; 7.4 ps; CMOS phase frequency detector; Gbit/s clock recovery; RMS jitter; bang-bang frequency detector; frequency acquisition range; giga-bit/s operation; lock acquisition; low-jitter detector; phase detector; Circuits; Clocks; Image edge detection; Jitter; Optical signal processing; Phase detection; Phase frequency detector; Switches; Timing; Voltage-controlled oscillators;
Conference_Titel :
Design of Mixed-Mode Integrated Circuits and Applications, 1999. Third International Workshop on
Conference_Location :
Puerto Vallarta
Print_ISBN :
0-7803-5588-1
DOI :
10.1109/MMICA.1999.833606
