DocumentCode
1857278
Title
Design of domino CMOS cells under delay constraint
Author
Zamudio, Alvaro ; Champac, Victor H. ; Sarmiento-Reyes, Arturo
Author_Institution
Inst. Nacional de Astrofisica, Opt. y Electron., Puebla, Mexico
fYear
1999
fDate
1999
Firstpage
106
Lastpage
109
Abstract
Simple expressions to estimate the delay and power consumption of domino gates have been developed. Using these expressions design guidelines are established for domino cells under a specified delay. It has been found that there is a trade-off between the power consumption and noise margin for domino cells designed for a specified delay. A good correspondence exists between the theoretical and simulated results
Keywords
CMOS logic circuits; delay estimation; integrated circuit noise; logic design; logic gates; delay constraint; design guidelines; domino CMOS cells; noise margin; power consumption; specified delay; CMOS logic circuits; Capacitance; Delay estimation; Energy consumption; Feedback; Logic design; Logic devices; Logic gates; MOS devices; MOSFETs;
fLanguage
English
Publisher
ieee
Conference_Titel
Design of Mixed-Mode Integrated Circuits and Applications, 1999. Third International Workshop on
Conference_Location
Puerto Vallarta
Print_ISBN
0-7803-5588-1
Type
conf
DOI
10.1109/MMICA.1999.833610
Filename
833610
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