Title :
14nm FDSOI upgraded device performance for ultra-low voltage operation
Author :
Weber, O. ; Josse, E. ; Mazurier, J. ; Degors, N. ; Chhun, S. ; Maury, P. ; Lagrasta, S. ; Barge, D. ; Manceau, J.-P. ; Haond, M.
Author_Institution :
LETI, CEA, Crolles, France
Abstract :
A performance upgrade of our 14nm FDSOI technology is reported in this paper. Compared to our previous 14nm FDSOI assessment, a -17% delay at the same leakage is demonstrated. We show that the AC performance of 28nm FDSOI at a 0.9V supply voltage is reached at 0.6V in 14nm FDSOI technology. This corresponds to a 50% increase in frequency at the same dynamic power, or a 65% power saving at the same operation frequency. The transistors are optimized to provide better drive current and, for the first time, a novel SiBCN low-k spacer material is successfully integrated in a gate-first FDSOI technology, providing a 10% reduction in gate-to-source/drain parasitic capacitance.
Keywords :
MOSFET; boron compounds; carbon compounds; low-k dielectric thin films; silicon compounds; silicon-on-insulator; AC performance; SiBCN low-k spacer material; drive current; dynamic power; gate-first FDSOI technology; gate-to-source-drain parasitic capacitance; power saving; size 14 nm; size 28 nm; ultra-low voltage operation; voltage 0.6 V; voltage 0.9 V; Capacitance; Delays; Logic gates; MOS devices; Performance evaluation; Silicon compounds; Transistors;
Conference_Titel :
VLSI Technology (VLSI Technology), 2015 Symposium on
Conference_Location :
Kyoto
DOI :
10.1109/VLSIT.2015.7223664
