Title :
Confined Epitaxial Lateral Overgrowth (CELO): A novel concept for scalable integration of CMOS-compatible InGaAs-on-insulator MOSFETs on large-area Si substrates
Author :
Czornomaz, L. ; Uccelli, E. ; Sousa, M. ; Deshpande, V. ; Djara, V. ; Caimi, D. ; Rossell, M.D. ; Erni, R. ; Fompeyrine, J.
Author_Institution :
Zurich Lab., IBM Res. GmbH, Rüschlikon, Switzerland
Abstract :
We report on the first demonstration of the CMOS-compatible integration of high-quality InGaAs on insulator (InGaAs-OI) on Si substrates by a novel concept named Confined Epitaxial Lateral Overgrowth (CELO). This method, based on selective epitaxy, only requires the use of standard large-area silicon substrates and typical CMOS processes. It enables the fabrication of InGaAs-OI starting from both bulk and SOI Si wafers. The InGaAs epitaxial structures are characterized by a very low defectivity, and can fulfill the requirements of both ultra-thin-body and fins-based advanced CMOS nodes. Gate-first self-aligned FinFETs (100-nm-long gate, 50-nm-wide fins and 250-nm-wide plug-contacts) with excellent electrical characteristics comparable to start-of-the-art InGaAs MOSFETs on Si are demonstrated, highlighting that this new concept has significant potential to enable introduction of high-mobility channel materials in high-volume manufacturing of advanced CMOS nodes.
Keywords :
III-V semiconductors; MOSFET; epitaxial growth; gallium arsenide; indium compounds; CELO; CMOS compatible process; InGaAs-SiO2-Si; MOSFET; confined epitaxial lateral overgrowth; fins based advanced CMOS node; gate first self-aligned FinFET; large area substrates; scalable integration; selective epitaxy; ultrathin body based advanced CMOS node; Epitaxial growth; III-V semiconductor materials; Indium gallium arsenide; Indium phosphide; Logic gates; Silicon; Substrates;
Conference_Titel :
VLSI Technology (VLSI Technology), 2015 Symposium on
Conference_Location :
Kyoto
DOI :
10.1109/VLSIT.2015.7223666