Buffer design trade-offs for single electron logic gates

Networks of buffered Threshold Logic Gates (TLG) implemented in Single Electron Tunneling technology have previously been demonstrated to operate correctly for a wide range of logic circuits. Given the complexity of the buffered TLG design, the TLG and the buffer are typically designed and optimized separately. In this paper we propose a method to design the TLG and the buffer separately while optimizing the compound design. First, we analyze the impact of the buffer on the TLG switching behavior. Second, we introduce a general buffer design methodology. Third, we presents a set of buffer implementations and demonstrate their impact on an example TLG.