Test Generation for State Retention Logic

As low power designs with multiple switchable power domains become more common, there is a need to ensure that the low power component structures in the design -such as isolation cells, state retention logic, and level shifters - are robustly tested during manufacturing test. This paper describes some of the challenges involved in testing low power components like state retention logic and proposes a novel method for testing them by cycling through the power modes of the chip to test their retention capability.