On-Chip Test Generation Mechanism for Scan-Based Two-Pattern Tests

We propose a new on-chip embedding mechanism to improve fault coverage in scan-based delay test. The initialization vector is shifted into the scan chain, and then the activation vector is generated by selectively inverting some bits to be loaded into the scan chain. Many scan-based delay test techniques do not provide good fault coverage as many valid test pattern pairs cannot be launched. The proposed approach provides a mechanism to modify activation vectors so that desired test pattern pairs can be launched. A formal design procedure for the embedded mechanism is presented. Experimental results show that, compared with previous work, the proposed method improves delay fault coverage with small area overhead.