Demonstration of p-type In0.7Ga0.3As/GaAs0.35Sb0.65 and n-type GaAs0.4Sb0.6/In0.65Ga0.35As complimentary Heterojunction Vertical Tunnel FETs for ultra-low power logic

Author

Pandey, R. ; Madan, H. ; Liu, H. ; Chobpattana, V. ; Barth, M. ; Rajamohanan, B. ; Hollander, M.J. ; Clark, T. ; Wang, K. ; Kim, J.-H. ; Gundlach, D. ; Cheung, K.P. ; Suehle, J. ; Engel-Herbert, R. ; Stemmer, S. ; Datta, S.

Author_Institution

Pennsylvania State Univ., University Park, PA, USA

fYear

2015

fDate

16-18 June 2015

Abstract

Extremely scaled high-k gate dielectrics with high quality electrical interfaces with arsenide (As) and antimonide (Sb) channels are used to demonstrate complimentary `all III-V´ Heterojunction Vertical Tunnel FET (HVTFET) with record performance at |V_DS|=0.5V. The p-type TFET (PTFET) has I_ON =30μA/μm and I_ON/I_OFF =10⁵, whereas the n-type TFET (NTFET) has I_ON =275μA/μm and I_ON/I_OFF=3×10⁵, respectively. NTFET shows 55mV/decade switching slope (SS) while PTFET shows 115mV/decade SS in pulsed mode measurement. Vertical TFET offers 77% higher effective drive strength than Si-FinFET for given inverter standard cell area. Energy-delay performance of TFET shows gain over CMOS for low V_DD logic applications.

Keywords

CMOS logic circuits; III-V semiconductors; MOSFET; field effect transistors; gallium arsenide; indium compounds; CMOS; FinFET; GaAs_0.4Sb_0.6-In_0.65Ga_0.35As; HVTFET; III-V heterojunction vertical tunnel FET; In_0.7Ga_0.3As-GaAs_0.35Sb_0.65; PTFET; VDD logic; complimentary heterojunction vertical tunnel FET; electrical interfaces; high-k gate dielectrics; n-type TFET; p-type TFET; switching slope; ultra-low power logic; voltage 0.5 V; Benchmark testing; FinFETs; Inverters; Layout; Logic gates; Silicon; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology (VLSI Technology), 2015 Symposium on

Conference_Location

Kyoto

ISSN

0743-1562

Type

conf

DOI

10.1109/VLSIT.2015.7223676

Filename

7223676