DocumentCode :
1857662
Title :
Level-Testability of Multi-operand Adders
Author :
Kito, Nobutaka ; Takagi, Naofumi
Author_Institution :
Dept. of Inf. Eng., Nagoya Univ., Nagoya
fYear :
2008
fDate :
24-27 Nov. 2008
Firstpage :
257
Lastpage :
260
Abstract :
Level-testability of multi-operand adders consisting of carry save adders is shown by showing test design for them. A multi-operand adder is a main part of a multiplier. 6L+2 patterns are sufficient to test a multi-operand adder under cell fault model, where L denotes the depth of the multi-operand adder. A test method of the multi-operand adder used as a partial product compressor in a multiplier is also shown. This result gives an upper bound of the number of required test patterns for a multi-operand adder in any multiplier.
Keywords :
adders; carry logic; logic testing; multiplying circuits; carry save adders; cell fault model; level-testability; multioperand adders test design; multiplier; partial product compressor; test patterns; Adders; Arithmetic; Birth disorders; Circuit faults; Circuit testing; Design engineering; Logic gates; Logic testing; Upper bound; Very large scale integration; Wallace multiplier; level-testability; multi-operand adder; multiplier;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Asian Test Symposium, 2008. ATS '08. 17th
Conference_Location :
Sapporo
ISSN :
1081-7735
Print_ISBN :
978-0-7695-3396-4
Type :
conf
DOI :
10.1109/ATS.2008.40
Filename :
4711593
Link To Document :
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