Efficient parallel implementation of motion estimation on the Computational RAM architecture

Motion estimation is the most computationally intensive task in present video compression standards. Parallel processing has proved to be an efficient approach for similar kinds of applications. In this paper, we propose two parallel implementations of block-based motion estimation for a massively-parallel, processor-in-memory hardware architecture known as Computational RAM (C-RAM). Our simulation study showed that, although the massive parallelism of C-RAM does potentially have great benefits, the use of embedded DRAM and bit-serial arithmetic reduced the achievable speed-up to about 4 compared to 733 MHz Pentium III machine.