DocumentCode :
1857828
Title :
Enabling Multithreading on CGRAs
Author :
Shrivastava, Aviral ; Pager, Jared ; Jeyapaul, Reiley ; Hamzeh, Mahdi ; Vrudhula, Sarma
Author_Institution :
Compiler Microarchiteture Lab., Arizona State Univ., Tempe, AZ, USA
fYear :
2011
fDate :
13-16 Sept. 2011
Firstpage :
255
Lastpage :
264
Abstract :
Coarse-Grained Reconfigurable Arrays or CGRAs are programmable fabrics that promise both high performance and high power efficiency. Traditionally, CGRAs were used to accelerate extremely-embedded systems, and were typically manually programmed. However, as CGRAs are conceived to be used as more general-purpose accelerators, there is a need to develop software tools and capabilities. Much work has been done on developing compiler techniques for CGRAs, making programming them easier, however, there is no support for multithreading. As an accelerator to a multithreaded processor, CGRAs now are restricted to accelerating only one kernel of one thread running on the processor at any point in time. Supporting multithreading is difficult, since the start times and end times of threads are dynamic in nature, while CGRAs are statically scheduled. In this paper, we propose a strategy to do multithreading on a CGRA. The chief capability that we develop is a scheme to quickly transform an existing application mapping using the entire CGRA to one using only a fraction of it. Our experimental results on kernels from multimedia applications demonstrate that multithreading support can improve the total throughput of a CGRA by over 30%, 75%, and 150% on 4×4, 6×6, and 8×8 CGRAs, respectively, compared to single-threaded methods.
Keywords :
embedded systems; multi-threading; multiprocessing systems; power aware computing; reconfigurable architectures; CGRA; coarse grained reconfigurable arrays; extremely embedded system; multimedia applications; multithreaded processor; power efficiency; programmable fabrics; Acceleration; Instruction sets; Kernel; Multithreading; Registers; Runtime; Schedules; CGRA; CGRA mapping technique; compiler optimization; dynamic threading; low power; multithreading; page-based mapping; processor accelerator; runtime scheduling; scheduling technique;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel Processing (ICPP), 2011 International Conference on
Conference_Location :
Taipei City
ISSN :
0190-3918
Print_ISBN :
978-1-4577-1336-1
Electronic_ISBN :
0190-3918
Type :
conf
DOI :
10.1109/ICPP.2011.77
Filename :
6047194
Link To Document :
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