DocumentCode
1857868
Title
Optimal chip sizing for hybrid-WSI
Author
Singh, P. ; Landis, D.L.
Author_Institution
Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA
fYear
1994
fDate
19-21 Jan 1994
Firstpage
374
Lastpage
386
Abstract
The inter-chip delay penalty for hybrid-WSI and MCM designs is much lower than that for printed wiring boards. Consequently, the system partitioning and die size optimization problems must be attacked using a different set of parameters. This paper develops a new figure of merit for optimal HWSI/MCM chip sizing based upon system quality level, cost, and silicon efficiency. The figure of merit is then applied to a 500k gate MCM case study
Keywords
VLSI; circuit layout CAD; hybrid integrated circuits; logic CAD; logic arrays; multichip modules; 500 KB; ASIC; MCM designs; Si; Si efficiency; cost; die size optimization; figure of merit; hybrid-WSI; inter-chip delay penalty; optimal HWSI/MCM chip sizing; optimal chip sizing; printed wiring boards; system partitioning; system quality level; Analytical models; Cost function; Delay; Integrated circuit interconnections; Logic gates; Microelectronics; Pins; Silicon; Very large scale integration; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Wafer Scale Integration, 1994. Proceedings., Sixth Annual IEEE International Conference on
Conference_Location
San Francisco, CA
Print_ISBN
0-7803-1850-1
Type
conf
DOI
10.1109/ICWSI.1994.291231
Filename
291231
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