Integrated diagnosis and reconfiguration process for defect tolerant WSI processor arrays

This paper presents a new technique for constructing a fault-free subarray from a defective WSI (wafer scale integration) processor array based on an integrated diagnosis and reconfiguration (IDAR) method. In a traditional yield enhancement approach, it diagnoses all units first and then the status (faulty or fault-free) of all units are passed to the reconfiguration algorithm for a possible reconfiguration solution. The basis of the IDAR method is that reconfiguration can be performed under partial diagnosis information. Systematic analysis has been used to formulate the IDAR process and to estimate the minimal size of a target array at which we need to diagnose all units. We also compare the yield enhancement cost of our approach with that of other strategies