DocumentCode
1858006
Title
Fault tolerant multicube pipeline processor
Author
Mori, Hideki ; Uehara, Minoru
Author_Institution
Dept. of Inf. & Comput. Sci., Toyo Univ., Japan
fYear
1994
fDate
19-21 Jan 1994
Firstpage
334
Lastpage
341
Abstract
This paper describes the architecture of fault tolerant pipeline processors. It uses multicube interconnection and voting based on cell reliability. Our architecture, featuring majority voting of results and reliability assessment to cells, ensures higher performance over conventional approaches in fault tolerance
Keywords
VLSI; circuit reliability; fault tolerant computing; microprocessor chips; multiprocessor interconnection networks; parallel architectures; pipeline processing; architecture; cell reliability; fault tolerant processor; majority voting; multicube interconnection; multicube pipeline processor; Clocks; Computer architecture; Concurrent computing; Fault tolerance; Manufacturing processes; Parallel processing; Pipeline processing; Redundancy; Timing; Voting;
fLanguage
English
Publisher
ieee
Conference_Titel
Wafer Scale Integration, 1994. Proceedings., Sixth Annual IEEE International Conference on
Conference_Location
San Francisco, CA
Print_ISBN
0-7803-1850-1
Type
conf
DOI
10.1109/ICWSI.1994.291240
Filename
291240
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