Title :
Fault tolerant multicube pipeline processor
Author :
Mori, Hideki ; Uehara, Minoru
Author_Institution :
Dept. of Inf. & Comput. Sci., Toyo Univ., Japan
Abstract :
This paper describes the architecture of fault tolerant pipeline processors. It uses multicube interconnection and voting based on cell reliability. Our architecture, featuring majority voting of results and reliability assessment to cells, ensures higher performance over conventional approaches in fault tolerance
Keywords :
VLSI; circuit reliability; fault tolerant computing; microprocessor chips; multiprocessor interconnection networks; parallel architectures; pipeline processing; architecture; cell reliability; fault tolerant processor; majority voting; multicube interconnection; multicube pipeline processor; Clocks; Computer architecture; Concurrent computing; Fault tolerance; Manufacturing processes; Parallel processing; Pipeline processing; Redundancy; Timing; Voting;
Conference_Titel :
Wafer Scale Integration, 1994. Proceedings., Sixth Annual IEEE International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-1850-1
DOI :
10.1109/ICWSI.1994.291240
