Integration scale increase of processor-arrays by using hierarchical redundancy

Author

Tsuda, Nobuo

Author_Institution

NTT Network Inf. Syst. Labs., Tokyo, Japan

fYear

1994

fDate

19-21 Jan 1994

Firstpage

324

Lastpage

333

Abstract

This paper specifies the relationships between WSI array structures and the maximum WSI integration scales possible when using hierarchical k-out-of-n redundancy configurations having expanded hierarchical levels. An estimate using five kinds of one-dimensional/two-dimensional array-connection models indicates that four-level redundancy configurations can increase the maximum possible integration scales 4 to 64 times over that achieved by single-level configurations according to the complexity of the array-connections. This feature is based on the distribution of defect-tolerance load into the hierarchical structures enhanced by expanding the hierarchical levels

Keywords

VLSI; cellular arrays; circuit reliability; redundancy; WSI array structures; defect-tolerance load; four-level redundancy configurations; hierarchical redundancy; integration scale increase; one-dimensional array-connection models; processor-arrays; two-dimensional array-connection models; Binary trees; Circuits; Information systems; Laboratories; Poisson equations; Redundancy; Routing; Switches; Testing; Wafer scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Wafer Scale Integration, 1994. Proceedings., Sixth Annual IEEE International Conference on

Conference_Location

San Francisco, CA

Print_ISBN

0-7803-1850-1

Type

conf

DOI

10.1109/ICWSI.1994.291241

Filename

291241