Test and reconfiguration experiments for a defect-tolerant large area monolithic multiprocessor system

The results of test and self-configuration of an experimental large area chip are described. The chip features all the logic required for the global test and configuration of a coarse-grained MIMD multiprocessor system. These structures are implemented on the 16 cm² Large Area Integrated Circuit 1 (LAIC 1). This chip utilizes different redundancy and reconfiguration concepts: 1) A defect-tolerant configuration network provides the connections of the modules. 2) System access is provided by a multiple-defect tolerant unidirectional scan path. 3) A repair of the primary I/O-buses is performed by programming laser fuses and anti-fuses. 4) The use of TMR for system clock and dual-rail signals for control lines enables an initial access to the system without laser repair. The results presented in this paper show, that all the proposed redundancy and reconfiguration concepts together provide a suitable scheme for the test and configuration of a large area chip containing coarse-grained modules with high module connectivity. These schemes have been proven to work even under adverse conditions such as large defects and high defect densities