3DVLSI with CoolCube process: An alternative path to scaling

Author

Batude, P. ; Fenouillet-Beranger, C. ; Pasini, L. ; Lu, V. ; Deprat, F. ; Brunet, L. ; Sklenard, B. ; Piegas-Luce, F. ; Casse, M. ; Mathieu, B. ; Billoint, O. ; Cibrario, G. ; Turkyilmaz, O. ; Sarhan, H. ; Thuries, S. ; Hutin, L. ; Sollier, S. ; Widiez, J

Author_Institution

LETI, CEA, Grenoble, France

fYear

2015

fDate

16-18 June 2015

Abstract

3D VLSI with a CoolCube™ integration allows vertically stacking several layers of devices with a unique connecting via density above a million/mm². This results in increased density with no extra cost associated to transistor scaling, while benefiting from gains in power and performance thanks to wire-length reduction. CoolCube™ technology leads to high performance top transistors with Thermal Budgets (TB) compatible with bottom MOSFET integrity. Key enablers are the dopant activation by Solid Phase Epitaxy (SPE) or nanosecond laser anneal, low temperature epitaxy, low k spacers and direct bonding. New data on the maximal TB bottom MOSFET can withstand (with high temperatures but short durations) offer new opportunities for top MOSFET process optimization.

Keywords

CMOS integrated circuits; annealing; epitaxial growth; integrated circuit bonding; semiconductor doping; three-dimensional integrated circuits; 3D VLSI; CoolCube process; MOSFET process optimization; alternative scaling path; direct bonding; dopant activation; high performance top transistor; low temperature epitaxy; low-k spacers; nanosecond laser anneal; solid phase epitaxy; thermal budget; vertical layer stacking; Annealing; Epitaxial growth; MOSFET; Three-dimensional displays; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology (VLSI Technology), 2015 Symposium on

Conference_Location

Kyoto

ISSN

0743-1562

Type

conf

DOI

10.1109/VLSIT.2015.7223698

Filename

7223698