DocumentCode :
1858183
Title :
DCScan: A Power-Aware Scan Testing Architecture
Author :
Dai, Gui ; You, Zhiqiang ; Kuang, Jishun ; Huang, Jiedi
Author_Institution :
Coll. of Comput. & Commun., Hunan Univ., Changsha
fYear :
2008
fDate :
24-27 Nov. 2008
Firstpage :
343
Lastpage :
348
Abstract :
This paper proposes a novel power-aware scan architecture: DCScan. In this architecture, the compatible scan cells are grouped into the same segment. Test data propagation in DCScan includes two parts: data copying and data shifting. There is no scan shift-in transition during data copying. Experimental results show our approach can achieve low test power, low wiring overhead and low test response data volume.
Keywords :
design for testability; integrated circuit testing; logic testing; DCScan; data copying; data shifting; power-aware scan testing architecture; scan cells; test data propagation; Circuit testing; Computer architecture; Costs; Design for testability; Educational institutions; Integrated circuit testing; Power dissipation; Software testing; Switches; Wiring; compatible scan cells; full scan testing; low power testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Asian Test Symposium, 2008. ATS '08. 17th
Conference_Location :
Sapporo
ISSN :
1081-7735
Print_ISBN :
978-0-7695-3396-4
Type :
conf
DOI :
10.1109/ATS.2008.61
Filename :
4711615
Link To Document :
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