Cycles analysis for testability of WSI sequential architectures

Author

Bombana, M. ; Buonanno, G. ; Cavalloro, P. ; Ferrandi, F. ; Sciuto, D. ; Zaza, G.

Author_Institution

DRSC-SM, ITALTEL SIT, Milan, Italy

fYear

1994

fDate

19-21 Jan 1994

Firstpage

188

Lastpage

197

Abstract

Testability analysis can he performed through classification of all possible simple interconnection topologies, definition of testability conditions on the functions performed by the cells composing the circuit and identification of the composition rules of such interconnections and of the testability conditions determined. This approach works well whenever feed-forward architectures are studied. Application of such approach to irregular architectures with cycles (signal feedbacks) is presented in this paper

Keywords

VLSI; design for testability; fault tolerant computing; reconfigurable architectures; sequential machines; WSI sequential architectures; composition rules; feed-forward architectures; interconnection topologies; irregular architectures; signal feedbacks; testability; Automatic testing; Circuit faults; Circuit testing; Circuit topology; Feedback; Feedforward systems; Integrated circuit interconnections; Performance analysis; Performance evaluation; Sequential analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Wafer Scale Integration, 1994. Proceedings., Sixth Annual IEEE International Conference on

Conference_Location

San Francisco, CA

Print_ISBN

0-7803-1850-1

Type

conf

DOI

10.1109/ICWSI.1994.291252

Filename

291252