Title :
Design for testability issues in the implementation of sequential array architectures
Author :
Bezzi, G. ; Bolchini, C. ; Bolzoni, I. ; Cantu, S. ; Fummi, F. ; Sciuto, D.
Author_Institution :
Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy
Abstract :
New design for testability techniques aiming at overcoming the problem of testing array architectures composed of sequential cells are proposed. Two strategies have been envisioned: structural DFT techniques whose goal is to guarantee controllability and observability of the cell, and functional techniques aiming at defining an easily testable implementation at the FSM level and then synthesizing the modified functional description. Evaluation of the two classes of strategies on benchmarks are provided
Keywords :
cellular arrays; controllability; design for testability; logic arrays; logic design; logic testing; observability; sequential circuits; FSM level; controllability; design for testability; functional techniques; observability; sequential array architectures; structural DFT techniques; testable implementation; Benchmark testing; Controllability; Design for testability; Error correction; Explosions; Hardware; Observability; Process design; Sequential analysis; Test pattern generators;
Conference_Titel :
Wafer Scale Integration, 1994. Proceedings., Sixth Annual IEEE International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-1850-1
DOI :
10.1109/ICWSI.1994.291254
