Design of FSM with Concurrent Error Detection Based on Viterbi Decoding

In this paper a new technique for designing finite state machines with concurrent error detection is presented using convolutional codes. In order to correct the fault, we propose a novel scheme which can not only detect but also correct errors occurred in FSM transition. More specifically, we demonstrate how the checker using maximum likelihood decoding can correct single-bit error and get 3dB higher of asymptotic coding gain than previous techniques, also we analysis bit error rate performance for Viterbi decoding of convolutional code. Moreover, we realize the IP core of the self-checking module by SMIC 0.25 mum CMOS technology and also simulate its function in FPGA .