Title :
Resistivity of copper interconnects beyond the 7 nm node
Author :
Pyzyna, A. ; Bruce, R. ; Lofaro, M. ; Tsai, H. ; Witt, C. ; Gignac, L. ; Brink, M. ; Guillorn, M. ; Fritz, G. ; Miyazoe, H. ; Klaus, D. ; Joseph, E. ; Rodbell, K.P. ; Lavoie, C. ; Park, D.-G.
Author_Institution :
Thomas J. Watson Res. Center, IBM Res., Yorktown Heights, NY, USA
Abstract :
The resistivity of damascene copper is measured at pitch ranging down to 40 nm and copper cross-sectional area as low as 140 nm2. Metallization by copper reflow is demonstrated at 28 nm pitch with patterning by directed self-assembly (DSA). Extremely low line-edge-roughness (LER) is attained by surface reconstruction of a single crystal silicon mask. Variation of LER is found to have no impact on resistivity. A resistivity benefit is found for wires with nearly bamboo grain structure, offering the promise of improved performance beyond the 7 nm node if grain size can be controlled.
Keywords :
copper; electrical resistivity; integrated circuit interconnections; integrated circuit metallisation; self-assembly; Cu; copper cross-sectional area; copper interconnect resistivity; copper reflow metallization; damascene copper; directed self-assembly; line edge roughness; patterning; single crystal silicon mask; surface reconstruction; Annealing; Conductivity; Copper; Grain boundaries; Grain size; Scattering; Wires;
Conference_Titel :
VLSI Technology (VLSI Technology), 2015 Symposium on
Conference_Location :
Kyoto
DOI :
10.1109/VLSIT.2015.7223712
