Optimization of row decoder for 128×128 6T SRAMs

Most of the power dissipation in SRAMs is due to the leakage and it is approximately 40% of total power dissipation. The leakage power increases as we move towards the technology scaling unless effectively optimized circuit is introduced to keep the leakage under control. In this paper we report on the optimization of a row decoder in terms of power and area. The row decoder is designed using three pre-decoders and a second level circuitry. Comparison of the proposed row decoder is done with the existing architecture using two pre decoders in terms of power consumption. About 25% reduction in power dissipation is obtained in the proposed architecture.